ST says its new microprocessors balance application-class performance, real-time control, and power management.

STMicroelectronics recently announced new low-power, cost-efficient additions to its STM32 microprocessor portfolio: the STM32MP21 series.

The STM32MP31 targets smart homes, smart cities, and smart factories. Image (modified) used courtesy of STMicroelectronics

The devices extend the company’s STM32MP2 family, focusing on price-sensitive edge designs that still require application-class processing and real-time control. According to ST, the new MPUs may be particularly useful in smart factory equipment and infrastructure systems that face tight energy and bill-of-materials constraints.

Key Features of the STM32MP21 MCU

ST built the STM32MP21 series (datasheet linked) around a heterogeneous processing architecture that combines a single-core 64-bit Arm Cortex-A35 application processor with a 32-bit Arm Cortex-M33 microcontroller. The Cortex-A35 operates at up to 1.5 GHz and includes 32-KB instruction and 32-KB data L1 caches, along with a 128-KB L2 cache. To help support Linux operating systems, it also includes support for Armv8-A execution states, NEON SIMD acceleration, and TrustZone.

Alongside the application core, the MCU includes a Cortex-M33 running at up to 300 MHz with FPU and DSP extensions, TrustZone support, and a memory protection unit. This secondary core is intended to manage real-time control loops and low-power housekeeping tasks independently of the main operating system. 

The STM32MP31 power supply scheme. Image used courtesy of STMicroelectronics

Beyond compute, memory support is a major differentiator in the STM32MP21 lineup. The devices integrate controllers for DDR3L, DDR4, and LPDDR4 memories with a 16-bit interface, supporting up to 4 GB of external DRAM depending on memory type. It also includes DDR3L support, enabling designers to mitigate cost and supply risks associated with newer memory technologies. Internally, the MPUs provide 456 KB of SRAM distributed across AXI system RAM, AHB SRAM, retention RAM, and backup SRAM regions, some of which are protected with ECC for data integrity.

Finally, the device includes up to two gigabit Ethernet interfaces with time-sensitive networking (TSN) support, multiple USB 2.0 ports with embedded high-speed PHYs, and a wide range of serial interfaces, including I3C, I2C, SPI, USART, and CAN FD. For vision and display applications, selected variants integrate MIPI CSI-2 camera interfaces with an embedded image signal processing pipeline, as well as an LCD-TFT controller that can drive displays up to 1080p at 60 fps.

Heterogeneous MPUs for Edge Systems

For device designers, a main engineering challenge is delivering high-level software functionality without sacrificing real-time behavior or power efficiency. To solve this problem, engineers have started embracing heterogeneous MPUs that blend different core classes to balance power and performance.

Application cores such as the Cortex-A35 are optimized for running rich operating systems, complex networking stacks, and user-facing applications. However, they are less efficient when handling always-on monitoring or time-critical control loops, particularly in low-power states. Microcontroller cores, by contrast, excel at deterministic execution and power-saving operation in deep sleep or standby modes.

Many edge designs embrace heterogeneous architectures for their compute cluster. Image used courtesy of Witekio

By integrating both core types on a single die, heterogeneous MPUs allow designers to partition workloads based on their real-time power requirements. The microcontroller can remain active to monitor sensors or manage wake-up events while the application processor is powered down or clock-gated. When higher-level processing is required, the application core resumes operation without the latency and energy overhead associated with external supervisors or companion controllers.

This approach also simplifies system design. Shared memory, inter-processor communication hardware, and unified security architectures reduce software complexity compared to multi-chip solutions. As demands on edge devices continue to grow, heterogeneous MPUs offer a scalable way to balance performance and energy consumption in constrained edge envelopes.

Implications for the Cost-Aware Edge 

With the STM32MP21 series, ST is clearly targeting developers who need application-class capabilities but are constrained by cost and power. The new device is now available for purchase in production quantities and includes protection under ST’s 10-year longevity program. Evaluation boards, including the STM32MP215F-DK Discovery kit, are also available.