During the recent PCI-SIG Developers Conference in Santa Clara, Keysight Technologies, Diodes Incorporated, and Viavi Solutions each announced new PCIe 7.0 products. As device manufacturers start to adopt the standard, there are naturally shortcomings in the existing market and development ecosystem. Each of the three releases touches on one of these areas where engineers may currently lack dedicated tools.

Keysight PCIe 7.0 Receiver Test Application

One of the biggest obstacles for hardware designers using PCIe 7.0 is validating whether the receiver can reliably receive data at 128 GT/s. For earlier PCIe versions, designers manually stress-tested their receivers, but at 128 GT/s, that manual process has become untenable. 

Keysight Technologies announced a new PCIe 7.0 Receiver Test application that pairs the M8050A BERT family of test equipment, including the M8042A 120 GBaud pattern generator and M8043A error analyzer, with the N5991PB7A Receiver Test Automation software to automate PCIe 7.0 receiver validation.

Keysight’s N5991PB7A Receiver Test Automation software. Image used courtesy of Keysight Technologies

According to Keysight, engineers can use the N5991PB7A to calibrate the TP3 and TP2 receiver stress signals without manual intervention, producing consistent, repeatable results and exportable calibration reports for post-processing. The company designed the software’s automated processes to expose receiver weaknesses early in development, before they lead to compliance failures that require costly late-stage rework. When combined with Keysight's existing PCIe 7.0 transmitter test solution, the receiver test application provides engineers with end-to-end physical-layer coverage from transmitter to receiver across the full validation workflow.

Diodes PI6CG33A06 Clock Generator

Hardware designers building reliable PCIe 7.0 data links need to tightly control reference clock jitter, as 128 GT/s speeds magnify even small errors. To help them, Diodes Incorporated introduced the PI6CG33A06, a six-output clock generator that generates 25-MHz and 100-MHz reference clocks with RMS jitter below 30 fs. That jitter figure is well below the PCIe 7.0 specification maximum of 67 fs and below the 80-fs level defined by Intel’s CK440Q specification. 

With this jitter margin, the company claims, engineers using this chip should have more freedom to design complex boards like those found in advanced AI data centers.

Block diagram of Diodes’ PI6CG33A06 clock generator. Image used courtesy of Diodes Incorporated

In addition to the PI6CG33A06’s ultra-low jitter, Diodes also implemented a proprietary low-power, high-speed current-steering logic (LP-HCSL) technology with integrated termination. LP-HCSL, the company claims, reduces the chip’s clock-related power consumption by at least 50% compared to traditional HCSL solutions—a reduction that matters in high-density AI server racks. 

The clock generator’s design also eliminates up to 24 external resistors, reducing the bill of materials and freeing up precious board space. Because the chip supports Intel CK440Q-Lite specifications, Diodes says its product can help designers reuse existing server clock architectures while improving timing performance and overall system margin.

Viavi Xgig PCIe 7.0 Testing Platform

For hardware designers to conduct protocol analysis for PCIe 7.0, they need tools that can capture and decode traffic across the full PCIe stack, including protocols that run on the PCIe fabric alongside the base specification. Viavi Solutions’ new Xgig PCIe 7.0 protocol analysis testing platform, which includes analyzers, exercisers, and high-performance interposers, does just that. Viavi designed the platform to deliver full-stack analysis for PCIe, IDE, NVMe, and CXL 3.x and beyond, using the familiar Xgig Software Suite with Trace Control, Expert, and Serialytics.

Viavi Xgig PCIe 7.0 Testing Platform chassis. Image used courtesy of Viavi

Beyond base PCIe validation, Viavi built the platform to address broader testing challenges that chip, peripheral, and system developers face at 128-GT/s data rates. The company added features such as auto-tuning to reduce reboots during equalization, port bifurcation for concurrent multi-instance analysis sessions, and Python API scripting for automated error injection. According to Viavi, the company is one of the few test vendors with established expertise in PCIe compliance testing, a position that led it to commit dedicated resources to the PCIe 7.0 ecosystem.

What Engineers Can Access Now

For chip and system designers working toward PCIe 7.0 compliance, these new tools from multiple vendors reduce their dependence on any single supplier and provide the industry with a broader foundation for serious validation work on the next-generation standard.