Rambus recently announced a three-chip solution for high-performance clocked memory modules in AI PC desktops and laptops. Called the DDR5 9600 Client Memory Module Chipset, the solution comprises a Gen2 client clock driver (CKD02), a power-management IC (PMIC5120), and a Serial Presence Detect hub (SPD Hub).

DDR5 CSODIMM with CKD, PMIC, and SPD Hub. Image used courtesy of Rambus

Rambus believes that such a cohesive solution will help PC designers embrace DDR5 data rates above 6,400 MT/s to support growing AI throughput demands. 

DDR5 9600 Client Memory Module Chipset

Here's a breakdown of the three-part DDR5 9600 Client Memory Module Chipset.

First, the Gen2 client clock driver (CKD02) buffers the clock signal between the host controller and the DRAM devices, supporting data rates up to 9,600 MT/s and clock frequencies up to 4,800 MHz. Rambus engineered the device to provide up to four differential output clock pairs, with single- and dual-PLL modes for flexible deployment. The CKD02 operates at 1.1 V and is housed in a 5.8 mm x 2.3 mm FPBGA package.

Block diagram of the DDR5 DR5CKD2Gxx. Image used courtesy of Rambus

For power delivery, the PMIC5120 accepts a 4.25-V to 5.5-V bulk input and generates up to five distinct voltage rails for the DRAM and supporting components on the module. According to Rambus, the device achieves more than 90% peak efficiency with a 5-V input and a 1.1-V output. Moving power regulation to the module eliminates the IR drop at the motherboard connector, which Rambus says tightens voltage tolerances at the DRAM and supports higher data-rate targets.  

Rounding out the chipset, the SPD Hub manages module identification, configuration, and telemetry over I2C and I3C. The device carries 1,024 bytes of non-volatile memory and an integrated temperature sensor, operates at 1.8 V, and supports I3C Basic bus rates up to 12.5 MHz.

Module-Level Clock Conditioning

DDR5 introduced a structural change in power management by moving it from the motherboard to the module itself, reducing IR drop on high-current rails and improving voltage tolerance for the DRAM. A parallel evolution is now playing out for clock distribution. 

In conventional DDR4 and early DDR5 designs, the host controller drives the clock signal directly to each DRAM device on the module. But when engineers scale DDR5 above 6,400 MT/s, clock jitter, signal degradation, and timing instability accumulate along the traces between the host controller and each DRAM device on the module, resulting in extremely narrow timing margins. In response, the industry has embraced clocked memory modules (e.g., CUDIMM and CQDIMM for desktops, CSODIMM for laptops), which place a client clock driver on the module itself to condition and redistribute the clock before it reaches the DRAMs.

Increasing DDR5 data rates can deleteriously impact signal integrity. Image used courtesy of Tech4Tea

A client clock driver functionally intercepts the incoming clock, re-times it through an on-chip phase-locked loop (PLL), and distributes separate, conditioned clock pairs to each DRAM channel. Because the CKD sits on the module near the DRAM devices, the output trace lengths are short and tightly controlled. Meanwhile, the PLL absorbs jitter introduced earlier in the signal path before those contributions reach the DRAMs. 

Enabling AI PCs

AI workloads are only growing more demanding on client platforms, and that means memory bandwidth and capacity constraints will only become more acute. By offering a complete chipset for clocked module architectures like CUDIMM and CSODIMM, Rambus hopes to simplify the designer’s path to 9,600 MT/s operation and beyond.