In April of this year, IBM announced a strategic collaboration with Arm, promising to “shape the future of enterprise computing”. Now, almost five months later, the company unveiled the next-generation processor for its IBM Z and LinuxONE systems, marking the first mainframe silicon whose cores natively and concurrently execute Arm and IBM instructions.

IBM and Arm call their dual-architecture design "revolutionary" for its ability to bring Arm-native applications to IBM's mainframes and servers. 

IBM's Dual-Architecture Processor

Supporting a second instruction set architecture (ISA) in hardware typically incurs silicon area overhead. This is because most approaches place separate cores for each ISA on the same die and let software route work between them. Unfortunately, that arrangement splits cache, complicates scheduling, and confines each workload to its own pool of cores.

IBM instead built one core that decodes both. The company says the processor switches between z/Architecture and AArch64 within nanoseconds. Because the two ISAs share a pipeline, one set of specifications applies to both.

IBM fabricates the processor on a 2-nm process with 11 high-performance cores running above 5.7 GHz, compared with eight cores at 5.5 GHz in Telum II. Each core has a 36-MB private L2 cache. IBM assembles a 432-MB virtual L3 and a 3.5-GB virtual L4 from those private allocations. According to IBM, systems built on the processor scale to hundreds of cores and tens of terabytes of memory.

Floor plan of the dual-architecture processor. 

The Arm side is a full hardware implementation with 2,792 AArch64 instructions, including the SVE and SVE2 vector extensions, and carries Arm SystemReady certification. The core also reconciles the byte-order difference between the two architectures, since z/Architecture is big-endian and AArch64 is little-endian.

Alongside the general-purpose cores, IBM integrated an AI inference accelerator that the company positions for latency-sensitive work such as in-transaction fraud detection. A dedicated on-chip data processing unit (DPU) handles I/O acceleration, and other hardware blocks handle cryptography, compression, and sort operations.

Running Software for Two Instruction Sets

An ISA sets the contract between compiled software and the underlying hardware. Once developers compile a codebase against one ISA, the resulting binary carries intrinsic assumptions about register widths, memory ordering, and byte order that the processor must match. And, since enterprise teams compile decades of software against a single ISA and then validate it under audit, replatforming a mainframe application is a multi-year project.

IBM’s new solution supports two ISAs on a single core. 

Since moving that software to a second ISA would require recompiling and revalidating every application, system architects who need both ecosystems on a single machine have two options. First, they can install separate hardware for each ISA and pass data between the two systems over a network, which consumes floor space and adds latency at every hand-off. Or they can run one ecosystem under emulation, writing a binary translation layer that reads instructions targeting one architecture and maps them onto the host's native instructions at runtime. Translation works, but developers lose cycles, especially in code with tight branches and heavy memory traffic.

Neither option gives architects what they actually want: a single machine that runs both ecosystems at full speed. This was the impetus for IBM’s new device.

Changes for Enterprise Buyers

As part of the April collaboration, IBM and Arm said they would:

1. Extend virtualization so Arm software environments could run inside IBM's enterprise platforms
2. Meet enterprise requirements for high availability, security, and data sovereignty
3. Build shared technology layers to widen both software ecosystems

IBM’s latest processor executes the first two goals, and Arm argues the third follows, since its ecosystem spans more than 22 million developers whose cloud and AI software now has a path onto mainframe hardware.

So far, neither company has disclosed pricing, packaging, or a ship date. IBM describes the silicon as directed at future IBM Z and LinuxONE generations.