At Christmastime 1985, John Moussouris carried a circuit board from California to Prime Computer in Massachusetts. Prime had agreed to prepay $1.5 million to Moussouris's year-old startup, MIPS Computer Systems, if it could deliver a working chip running real code at a set clock rate by the holiday. Instead of the welcome he expected, Moussouris told a Computer History Museum panel in 2011 that he found an executive with a red nose and a sour expression who had signed off on the payment, certain that MIPS could never deliver. It had. 

Dr. John Moussouris. Image used courtesy of St. Cross College Oxford

The board carried the R2000, a 32-bit processor with 110,000 transistors on an 80 mm2die in 2 µm CMOS, the commercial version of a research project John Hennessy had run at Stanford University since 1981. Its five-stage pipeline is the one computer-architecture students have been drawing ever since.

A Class Project With No Interlocks

MIPS began in spring 1981 as a Stanford VLSI design class taught by Hennessy. The acronym stood for Microprocessor Without Interlocked Pipe Stages. A pipelined processor normally carries hardware to notice when one instruction needs a result the previous one has not yet produced, and to stall until it arrives. The Stanford chip had none, and the group's 1982 paper said so: the machine "provides no pipeline interlock hardware; this function must be provided by software." 

Diagram of the MIPS R2000 CPU and FPU. Image used courtesy of Imperial College London

A compiler pass the team called the reorganizer went through the generated code and, wherever one instruction depended on the previous one, moved an unrelated instruction in between. When nothing unrelated was available, it inserted a no-op. Branches worked the same way. By the time the chip knew whether a branch was taken, it had already fetched the next instruction, so the design executed it and left the compiler to fill it with something useful. With six pipeline stages, that would have meant two such instructions; in autumn 1981 the team cut the pipeline to five, so there was only one. 

The Stanford chip was nMOS, about 25,000 transistors, 16 registers, and a 4-MHz target. Working 3-µm parts came back from DARPA's MOSIS service in early 1984 and ran their first complete program, the eight queens puzzle, on February 20. Hennessy has said the pitch to venture capitalists at the time was hand-drawn slides with "nothing about analysis of the market." He, Moussouris, then on sabbatical from IBM, and Skip Stritter, a Motorola 68000 architect, incorporated MIPS Computer Systems in the summer of 1984, and the Mayfield Fund put in $1.5 million that October.

Not a Single Rectangle in Common

Moussouris has said the R2000 shared "not a single rectangle" with the Stanford layout, and that most of the differences came from turning a class project into a chip that could run Unix. It moved from nMOS to CMOS, doubled the register file to 32, and switched from word to byte addressing.

Stanford's 1984 report had put memory management off-chip because 4-µm nMOS couldn’t fit it; at 2 µm, the R2000 got a 64-entry fully associative TLB mapping 4-KB pages. Cache and floating-point didn’t fit in 110,000 transistors, so the R2000 drove up to 64 KB each of instruction and data cache in off-chip SRAM. Floating-point went to the R2010 coprocessor, and R2020 chips queued up to four pending writes to DRAM. It shipped in a 144-pin PGA at 8.3 MHz, 12.5 MHz, and 15 MHz.

The pipeline itself carried over unchanged. An instruction still moved through five stages: instruction fetch, register read, ALU, memory access, and write-back, with a new instruction entering every clock cycle, and the two hazards were still the compiler's problem. An instruction couldn’t use the result of the load immediately before it, so the compiler put an unrelated instruction or a no-op in that slot, and the instruction after a branch still executed whether or not the branch was taken. John Mashey, an early MIPS engineer, has pointed out that the chip did have interlocks on the multiply and divide result registers and on the floating-point unit, so that name was never quite literal.

MIPS had no fab of its own and had sent the design to VLSI Technology. Sierra Semiconductor, a San Jose startup, asked to run the masks as well and offered to do it for free, charging only if its yield turned out as good as VLSI's. MIPS taped out just before Thanksgiving 1985. 17 days later, Sierra delivered wafers with fully working devices, and for the following year, Moussouris said, nobody else managed to make the chip at all. Second sources arrived in December 1987, when MIPS licensed Integrated Device Technology, LSI Logic, and Performance Semiconductor.

Workstations and Textbooks

Carnegie Mellon's Software Engineering Institute clocked the R2000-based MIPS M/500 in 1987 at about 8 million instructions per second, roughly five times a VAX-11/780. Silicon Graphics had told Moussouris it was going with Fairchild's Clipper, then reversed course after a day of meetings between the two companies' engineers and put an 8-MHz R2000 board in the IRIS 4D/60 in 1987. Digital Equipment canceled its in-house PRISM RISC program in July 1988 and shipped its first RISC machine, the DECstation 3100, in January 1989, a 16.67-MHz R2000 system at $11,900.

Hennessy and David Patterson published “Computer Architecture: A Quantitative Approach” in 1990, while, in Hennessy's words, they "hid out at DEC WRL." Their undergraduate text, “Computer Organization and Design,” taught the R2000 and R3000 instruction set directly, using the SPIM simulator. 

Hennessy has said the 1990 book "took over as the standard textbook," and the two shared the 2017 Turing Award. The delay slots didn’t last as long, though. Mashey has called the load delay slot a mistake, and the MIPS II instruction set dropped the requirement. MIPS itself went to SGI in 1992, then Imagination Technologies, pivoted to RISC-V in 2021, and was acquired by GlobalFoundries in August 2025.

Did you learn pipelining from a MIPS diagram, or run code on an IRIS or DECstation? Tell us about it in the comments below.